Itanium Instructions

Only the instructions most likely to be encountered in user-mode code are detailed here. Instructions marked with an asterisk (*) are particularly important.

The general notation for instructions is:

(qp)    op...   dest = src1, src2, ...

where (qp) is the optional qualifying predicate, the ellipses (...) after the opcode are optional completers, dest is the destination (or destinations, for comparison operators), and src is the source.

Memory Access (Aligned)

An optional parameter after the comma performs a postincrement of the Rb register. For example, ld8 r1 = [r2], 8 loads a 64-bit value from the address in r2 and then increments the r2 register by 8.

An optional .nt# completer spcifies that the memory will not be accessed again for a while. Higher values of # indicate longer-term abandonment. (.nta is the most aggressive level.)

Again, an optional parameter after the comma performs a postincrement of the address register.

And again for floating-point registers.

Memory Access (Advanced/Speculated)

These were previously discussed.

Read and write a value that might have the NaT bit set. The numerical value is written as usual, and the NaT bit is saved/restored in the ar.unat special register. These allow you to speculate across procedure calls.

Verifying Speculated/Advanced Instructions

Clearing an advanced load means that you have no plans to check the load again.

Special Registers

Special registers, in general, can only be read from and written to. They do not take part in arithmetic computations and cannot be compared against directly.

The mask specifies which predicate registers should be loaded from register Ra. The bottom bit of the mask corresponds to predicate register p1, through bit 14 of the mask corresponding to predicate register p15. Bit 15 of the mask represents all the predicate registers p16 through p63. (Recall that predicate register zero is hard-wired to TRUE.)

Recall that the predicate register preservation rules are established by convention, so the only masks you are likely to see are -1 (restore all registers) and 0x801F (preserve all the usual registers).

Interlocked Instructions

Store Rc to [Rb] and return the original value in Ra.

Check if the value in [Rb] is equal to the special ar.ccv register. If so, store Rc to [Rb]; otherwise, leave it unchanged. In either case, return the original value of [Rb] in Ra.

Atomically adds Rc/n to [Rb], returning the previous value in Ra.

Control Flow

See the Control Flow section in Itanium Architecture for a description of the various completers.

There are other types of branch instructions as well, but these are not used as much.

Arithmetic

This shifts the first addend left by up to four positions before adding.

Note  There is no integer division or multiplication. See the Multiplication subsection in this section for a multiplication workaround. For division, you will have to convert to floating point.

Multiplication

There is a special floating-point format for handling integer multiplication.

The setf.sig and getf.sig instructions transfer between integer registers and floating-point registers (in the special form).

The xma instruction performs the operation on numbers in special form, and the result is also in special form.

There are four variations on the xma instruction. The .l version saves the low 64 bits of the result, the .h version saves the high 64 bits of the result, and the .u version performs an unsigned multiplication, rather than a signed multiplication.

For example, xma.lu performs the multiplication as two unsigned integers and saves the low 64 bits of the result.

Bits

The andcm instruction clears the bits specified by the last parameter.

The shx instructions do shifting. A more general form of shifting is performed by the extr and dep instructions.

The regular version of the extr (extract) instruction sign-extends the result, whereas the extr.u form zero-extends the result. The bit extraction instructions are also used to handle unaligned data.

The dep (deposit) instruction builds its output by taking the <n1, n2> part from Rb and the rest of Rc. Think of it as a masked blt.

The shrp (shift right pair) instruction treats Rb and Rc as a huge 128-bit value and extracts 64 bits of it into the Ra register.

Constants

Small numbers (up to 22 bits) can be loaded using add Ra = n, r0 instruction. Larger numbers require the movl instruction. This is one of the few instructions that takes up two slots.

Comparisons

See Comparisons section in Itanium Architecture for a detailed explanation.

The tbit instruction tests bit n in register Ra, setting both p1 and p2 accordingly.

Bit and Bytes

If there is no zero byte or word, the czx instruction sets the Ra register to 8 (czx1) or 4 (czx2).

Conversion

Idioms

You can rotate by doing a paired shift where the two input registers are the same.